1. Field of the Invention
The present invention relates to a MOS type semiconductor memory device, and more particularly to a MOS type semiconductor device having a MOS transistor and a capacitor cell which constitute a dynamic RAM.
2. Description of the Related Art
It is known to provide a MOS type semiconductor memory device having a MOS transistor and a stacked capacitor cell which constitute a dynamic RAM.
For example, JP-A-1-119054 (1989) discloses a MOS type semiconductor memory device in which a Si (silicon) substrate is formed with plural isolated-regions, and a memory cell including a MOS transistor and a stacked capacitor cell is formed in each of the regions.
In fabricating a MOS type semiconductor memory device, a gate electrode is formed with an intermediate gate insulating film on a main surface of a Si substrate of, for example, p-conductivity type at each isolated region. Then, N type impurities such as arsenic (As) are highly ion-implanted in predetermined regions of the Si substrate by using the gate electrode as a mask. The impurities are diffused and activated by heat treatment thereby forming source and drain of the MOS transistor.
Next, an inter-layer insulating film is formed on the entire surface so as to cover the gate electrode and the gate insulating film. Predetermined portions of the inter-layer insulating film and the gate insulating film are etched away to form a contact hole. A polycrystalline Si film doped with N type impurities such as arsenic (As) and phosphorus (P) is formed so as to cover the contact hole and the inter-layer insulating film thereby forming a conductive layer serving as a lower electrode (charge storage layer) of the stacked capacitor cell. In this case, the drain region is made sufficiently large so that it is exposed to the contact hole. Otherwise, in doping the poly Si film with the N type impurities, the highly doped diffused layer is formed immediately below the contact hole by diffusion of the N type impurities in the Si substrate so as to overlap with the drain region. Thus, an electric contact is made between the drain region and the lower electrode layer. Thereafter, a dielectric film and another conductive layer of a poly Si film doped with the N type impurities such as As or P which serves as an upper electrode of the stacked capacitor cell are formed successively on the lower electrode, thereby forming a stacked capacitor cell. The stacked capacitor cell and the MOS transistor constitute a MOS type semiconductor memory cell.
The MOS type semiconductor memory device thus formed has a tendency that an electric field concentrates on the junction between the highly doped diffused layer and the Si substrate or a P-N junction to increase a leak current therebetween. As a result, the conventional MOS type semiconductor memory device involves a problem that the data is not held in the memory cell for a sufficiently long time so that it is difficult to discriminate a charged state from a discharged state when the data is read out, resulting in a reading error.